The present invention relates to a semiconductor integrated circuit device having an electrostatic discharge (ESD) protection circuit, and more particularly, to a semiconductor integrated circuit device having an ESD protection circuit on its input side.
In recent years, semiconductor integrated circuit devices have been increasingly highly integrated in response to the progress in technologies for achieving scaling down and higher density in the process field. With the achievement of higher integration, semiconductor integrated circuits have become more susceptible to damages due to electrostatic discharge (hereinafter, called surges). For example, elements constituting an input circuit, an output circuit, an input/output (I/O) circuit, an internal circuit and the like are increasingly likely to be broken down, or degraded in performance, due to a surge intruding via a pad for external connection. To overcome this problem, semiconductor integrated circuits are provided with an electrostatic discharge (ESD) protection circuit for protecting such an input circuit, an output circuit, an I/O circuit, an internal circuit and the like from a surge.
FIG. 7 shows a circuit configuration of a conventional semiconductor integrated circuit device having ESD protection circuits (see Albert Z. H. Wang, “ON-CHIP ESD PROTECTION FOR INTEGRATED CIRCUITS”, Kluwer Academic Publishers, 2002, for example). As shown in FIG. 7, the conventional semiconductor integrated circuit device includes: a circuit 104 to be protected having an input circuit function, including an inverter that receives power supply from a power supply line 101 and a ground (GND) line 102 and is connected to an input pad 103 at its input terminal; a first ESD protection circuit 105 connected between the power supply line 101 and the input pad 103; and a second ESD protection circuit 106 connected between the input pad 103 and the GND line 102.
The first ESD protection circuit 105 has a p-type metal oxide semiconductor (PMOS) transistor 110 whose source and gate are connected to the power supply line 101 and whose drain is connected to the input pad 103, configured to allow a surge intruding via the input pad 103 to flow to the power supply line 101 to thereby protect the circuit 104 to be protected from the surge.
The second ESD protection circuit 106 has an n-type metal oxide semiconductor (NMOS) transistor 111 whose source and gate are connected to the GND line 102 and whose drain is connected to the input pad 103, configured to allow a surge intruding via the input pad 103 to flow to the GND line 102 to thereby protect the circuit 104 to be protected from the surge.
The circuit 104 to be protected has a PMOS transistor 112 whose source is connected to the power supply line 101, whose drain is connected to the output terminal of the circuit 104 to be protected and whose gate is connected to the input pad 103, and an NMOS transistor 113 whose source is connected to the GND line 102, whose drain is connected to the output terminal of the circuit 104 to be protected and whose gate is connected to the input pad 103.
In the conventional semiconductor integrated circuit configured as described above, a positive surge (plus surge) that intrudes from outside via the input pad 103 and flows between the input pad 103 and the GND line 102 can be allowed to escape to the GND line 102 with occurrence of breakdown of the NMOS transistor 111 constituting the second ESD protection circuit 106, to thereby protect the device 104 to be protected.
Reversely, a negative surge (minus surge) that intrudes from outside via the input pad 103 and flows between the input pad 103 and the power supply line 101 can be allowed to escape to the input pad 103 with occurrence of breakdown of the PMOS transistor 110 constituting the first ESD protection circuit 104, to thereby protect the device 104 to be protected.
However, the conventional semiconductor integrated circuit device having ESD protection circuits described above has the following problem. If a plus surge is applied to the input pad 103 while the GND line 102 is grounded, for example, the circuit 104 to be protected may be broken down due to scaling down in the semiconductor fabrication process.
The reason is that, with scaling down in the process, the gate oxide film of each MOS transistor included in the circuit 104 to be protected is thinned and thus decreases in withstand voltage. Therefore, the breakdown voltage of the NMOS transistor 111 in the second ESD protection circuit 106 may become higher than the withstand voltage of the gate oxide film of the NMOS transistor 113 in the circuit 104 to be protected.
In other words, the potential of the input pad 103 may exceed the withstand voltage of the gate oxide film of the NMOS transistor 113 in the circuit 104 to be protected before the NMOS transistor 111 in the second ESD protection circuit 106 is turned ON, and this may result in breakdown of the gate oxide film of the NMOS transistor 113 in the circuit 104 to be protected. Likewise, the PMOS transistor 112 in the protected circuit 104 may possibly be broken down if a negative surge is applied to the input pad 103 while the power supply line 101 is grounded.